1. Field of the Invention
The present invention relates to a semiconductor element and a semiconductor device.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor field effect transistors) are normally placed in an off-state to prevent currents from leaking by means of pn junctions. The primary causes of leak currents include subthreshold currents and reversed carrier recombination. Such currents are small but not negligible; they determine the data holding time of DRAMs (dynamic random access memories) and define their refresh cycles. Schemes proposed so far to minimize leak currents include the reduction of crystal defects with wafers subject to epitaxial growth, and complete depletion in the off-state by use of SOI (silicon on insulator) wafers.
There has been proposed a memory element structure called gain cells capable of operating as DRAM cells with reduced stored charges. The proposed structure involves electrically charging a memory node via a write transistor so that the stored charge in the node causes a separately provided read transistor to vary its threshold voltage, which represents a piece of data stored. Related conventional techniques include a structure using polycrystal silicon for write transistors as disclosed by H. Shichijo et al., Conference on Solid State Device and Materials, pp. 265-268, 1984; and a structure using polycrystal silicon for read transistors as proposed by S. Shukuri et al., IEEE International Electron Devices Meeting, pp. 1006-1008, 1992.
Other conventional techniques related to this invention include a single electronic memory utilizing polycrystal silicon as depicted by K. Yano et al., IEEE International Electron Devices Meeting, pp. 541-544, 1993, as well as by Ishii et at., IEEE International Solid-State Circuits Conferences, pp. 266-267, 1996. In the proposed electronic memory, polycrystal silicon thin films are used concurrently to form channels as current paths and storage regions for capturing electrons. A piece of data is retained when electrons captured by a storage region change the latter""s threshold voltage. What characterizes this technique is that a few electrons are enough to store one bit of data. Electrons are injected into a given storage region by applying a voltage of 12 V through 15 V to a gate electrode. To discharge the stored electrons requires applying a voltage of xe2x88x9210 V through xe2x88x9215 V to the gate electrode. The use of polycrystal silicon grains permits formation of a structure effectively smaller than the fabricated size. Memory elements in this structure are capable of operating at room temperature. A single transistor constitutes each memory element.
One of the guides to MOSFET micro-fabrication is the scaling law. According to this principle, reduction of the size to 1/K requires multiplying the substrate density by a factor of K. However, raising the substrate density narrows the depletion layer width and increases leaks from junctions. A solution to this problem involves the use of an SOI substrate for a complete depletion in the off-state. In that case, leak currents sill flow illustratively because of the reversed carrier recombination, although the currents are smaller than in ordinary substrates. At very advanced levels of micro-fabrication, uneven positions of impurities in channels can trigger the flow of leak currents. Efforts to design for a high threshold voltage can be defeated by a current path being formed at a voltage lower than the threshold voltage due to the uneven presence of impurities, with the current path condoning a flow of leak currents.
Ever-finer structures of memory cells in DRAMs, flash memories and other types of memories have translated into smaller memory cell areas than ever before. The trend has made it possible to implement ever-greater memory capacities. In particular, DRAMs with one transistor and one capacitor making up their basic structure have gained widespread acceptance as a memory device offering both high-speed performance and high degrees of integration. The growing scale of memories, however, requires longer refresh cycles. The trend thus presents a need for a low-leak FET structure. For the DRAMs, a simple-minded drive for more advanced micro-fabrication aimed at smaller memory cell areas entails narrowing areas of capacitors, reducing capacitance values of the capacitors and lowering their stored charges. Meanwhile, data lines are generally extended as the memory size increases. Since the data lines are subject to charging and discharging operations and should also be resistant to noise, the amount of stored charges cannot be too low. Hence the problem of having to devise for each new generation of DRAMs a novel scheme for building a three-dimensional capacitor structure or for enhancing the dielectric constant of capacitor insulating films.
One solution to the above problem is not directly to charge or discharge the data lines using cumulative charges but to accumulate electrical charges near transistor channels so as to vary the threshold voltage of transistors for data storage. Because the solution allows the data lines to be charged and discharged using drain currents of transistors, the problem above is bypassed and memory elements are easily reduced in size. The conventional three-transistor type DRAM has been proposed on the basis of the solution above. The three-transistor type DRAM needs to make its refresh cycle shorter than before because its amount of cumulative charges is smaller than in ordinary DRAMs. The refresh cycle is required to be shortened progressively the higher the degree of integration. This, it can be expected, will eventually result in another problem.
The EEPROM and flash memory are other memory elements that have electrical charges stored in the vicinity of transistor channels to vary the transistor threshold voltage for data retention. In operation, a high voltage is applied to a tunnel insulating film in order to inject electrons or holes into a floating gate. One disadvantage of this type of memory is that it takes time to write or read data because currents are made to flow through the insulating films. Since the operating voltage is high, it is necessary to prepare peripheral circuits of high dielectric strengths. Such peripheral circuits tend to occupy wider areas. In order to ensure reliable data retention under high-voltage application, the tunnel insulating film must at least have a thickness of a little less than 10 nm. That means the tunnel insulating film cannot be made thinner than that size while the elements are being scaled down, so that the short channel effect is getting more and more pronounced. Furthermore, the amount of currents flowing through tunnels varies considerably depending on the insulating film thickness and on the presence or absence of traps. This leads to significant variations in characteristics between memory elements.
It is therefore an object of the present invention to provide a semiconductor element operating on a threshold voltage controlling method not resorting to low leaks or to impurity injection; a scaled-down semiconductor memory device which uses such semiconductor elements and is capable of ensuring a sufficiently long refresh cycle for high-speed write operations; and a semiconductor device comprising such elements.
The invention envisages reducing leak currents and controlling a threshold voltage by taking advantage of the quantum-mechanical containment effect brought about in the direction of film thickness by use of a very thin semiconductor structure for channels.
In carrying out the invention, there is typically provided a semiconductor element comprising a transistor structure having a source region 200; see FIG. 23, a drain region 201, a channel region 202 for connecting the source region 200 and the drain region 201, and a control electrode 203 for controlling conductance of the channel region 202, wherein an average thickness of the channel region 202 is 5 nm at most. This semiconductor element is typically constituted as shown in FIG. 23 but is not limited thereby.
In carrying out the invention, there is also provided a semiconductor memory element wherein conductance between the source and drain of a read transistor is varied depending on the amount of stored electrical charges, the conductance variation being used to retain a piece of data, and wherein a channel of a transistor for electrically charging or discharging a charge accumulating region is made of a semiconductor 5 nm or less in thickness. This structure enables both high-speed data write performance and prolonged data retention. The thickness of transistor channels may be minimized as desired so long as film defects do not become apparent during fabrication processes.
In carrying out the invention, there is also provided a semiconductor element comprising: a read transistor structure made of a source region 7; see FIG. 1, a drain region 8, a semiconductor region 8 for interconnecting the source region 7 and the drain region 8, and a control electrode 5 for controlling conductance of the semiconductor region 6; a charge accumulating region 1 located near the semiconductor region 6 for interconnecting the source region 7 and the drain region 8; and a write transistor structure 1, 2, 3, 5 for either electrically charging or electrically discharging the charge accumulating region 1; wherein an amount of electrical charges stored in the charge accumulating region 1 changes conductance between the source region 7 and the drain region 8 in the read transistor structure, the conductance change being used for data storage; and wherein a channel of the write transistor structure is made of a semiconductor 5 nm at most in average thickness. This semiconductor element is typically constituted as shown in FIG. 1 but is not limited thereby.
The electrical conductivity of low-dimensional systems was heretofore discussed with a view to improving system mobility but was never talked about in terms of reducing leak currents in the off-state. To the inventors of this invention, it was not clear at the outset that with such a thin semiconductor film, the leak currents could be made smaller. To prove that the leak currents were actually reduced, the inventors experimentally fabricated semiconductor transistors, one of which is shown in FIGS. 20A and 20B. FIG. 20A is a cross-sectional view of the semiconductor transistor, and FIG. 20B is a top view of the same transistor. The experimentally fabricated transistor included a source region 103, a drain region 105 and a control electrode 106 made of n-type polycrystal silicon. A channel 104 in the semiconductor was a non-doped polycrystal silicon film with an average thickness of 3 nm. The channel was deposited in an amorphous state and crystallized later by a heating process. The channel thin line was 0.1 micron wide and 0.3 microns long, and the thickness of a gate oxide film in the transistor was 25 nm. FIG. 21A shows how a drain current varied when a drain voltage of the experimental semiconductor transistor was fixed to 1 V and its gate voltage was changed. FIG. 21B depicts how the drain current of the transistor varied over time when the drain voltage was fixed to 1 V and the gate voltage was fixed to xe2x88x920.5 V. Currents were measured by use of the HP4156 Parameter Analyzer available from Hewlett-Packard Co., and measurements were taken in the xe2x80x9clongxe2x80x9d measurement mode at room temperature. The measuring increment of the analyzer was 10 fA, and the measurements fluctuated between 0 and xe2x88x9210 fA. In view of the behavior of the current values, the fluctuating measurements were judged to represent not true currents but ambient noise. In other words, the leak currents were less than 10 fA. Further comparisons were made of leak currents between transistors fabricated experimentally with their average channel thickness varied from 3 nm to 5 nm to 8 nm. On transistors of each channel thickness, leak currents were measured when the drain voltage was set for 1 V and the gate voltage was set to be 1.5 V lower than a threshold voltage Vth for a drain current of 1 pA. Six transistors of each film thickness type were measured for leak currents, and the measurements were averaged and illustrated graphically in FIG. 39. As shown in FIG. 39, most measurements came below the measurable limit for the film thicknesses of 3 nm and 5 nm, while leak currents became measurable for the film thickness of 8 nm, rising by one order of magnitude. The results indicate that the film thickness is preferably less than 8 nm. Unlike the well-known single electronic memory constituted by polycrystal silicon, the experimentally fabricated transistors operated on a voltage as low as xc2x13 V or less. Whereas relatively thick gate oxide films (25 nm thick each) were used in the experiments, smaller operating voltages permit the use of a thinner film in view of dielectric strength. In such a case, the transistors can operate on a still lower voltage than ever. These preliminary considerations undertaken by the inventors formed a basis for conceiving this invention.
The invention also proposes a novel gain cell structure comprising: a substrate; a read transistor having a source region and a drain region formed illustratively as diffusion regions in the substrate, and a channel region for interconnecting the source region and the drain region; a charge accumulating region located near the channel region; and a write transistor for either electrically charging or electrically discharging the charge accumulating region; wherein at least part of a channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane (the widest surface) of the substrate.
In the gain cell structure above, the write transistor can be constituted without recourse to a diffusion layer. In a preferred structure, the semiconductor film is arranged to have an average thickness of 8 nm or less and more preferably under 5 nm when deposited on a side of a construct formed in a convex fashion on the principal plane of the substrate. A minimum film thickness may be determined as desired so long as film defects do not become apparent. Advantageous characteristics are available when the film thickness is 3 nm. The side of the construct is illustratively perpendicular to the principal plane of the substrate. The construct may double as a control electrode for the channel. The source and drain regions of the write transistor may be formed by films stacked on the principal plane of the substrate. In this structure, the current flowing through the channel of the write transistor passes along the surface of the semiconductor film constituting the channel and in an approximately perpendicular relation to the principal plane of the substrate.
In carrying out the invention, there is also provided a semiconductor memory element comprising: a substrate; a read transistor having a source region and a drain region formed in the substrate, and a channel region for interconnecting the source region and the drain region; a charge accumulating region located near the channel region; and a write transistor for either electrically charging or electrically discharging the charge accumulating region; wherein a source region, a drain region and a channel of the write transistor are formed by films deposited on a principal plane of the substrate, the source region and the drain region being spaced apart horizontally over the principal plane of the substrate. With this structure, the film making up the channel of the write transistor is constituted by a semiconductor preferably 8 nm or less and more preferably under 5 nm in average thickness. A minimum film thickness may be determined as desired so long as film defects do not become apparent. Advantageous characteristics are available when the film thickness is 3 nm. Preferably, the films constituting the source and drain regions of the write transistor are each arranged to be thicker than the film making up the channel of the write transistor. In such a constitution, the current flowing through the channel of the write transistor passes along the surface of the semiconductor film constituting the channel and in an approximately perpendicular relation to the principal plane of the substrate.